A conventional switch-mode power supply is illustrated in the block diagram of FIG. 1. The voltage applied to load 10 at the VOUT node is regulated by the power supply circuit. The load is connected in series with a signal responsive switch 12, the series circuit connected across output capacitor 14. The capacitor and switch are both directly connected to the ground power supply terminal. The other power supply terminal, VIN, is connected to the VOUT node through inductance 16 and diode 18. VSW, the junction of the inductance and diode, is connected through signal responsive switch 20 to ground via current-sense resistor 13. Signal responsive switches such as 12 and 20 are typically electronic switches having gate activation. Signal responsive switch 12 is operable in response to a pulse width modulated signal PWM. Signal responsive switch 20 is operable in response to a feedback control circuit that comprises error amplifier 22, capacitor 24, oscillator 11, comparator 15, and latch 28. A reference voltage VREF is applied to a first input of the error amplifier 22. The voltage at the VOUT node, or a fraction thereof, is applied to the second input of the error amplifier. Capacitor 24 is charged and discharged by the output of the error amplifier.
FIG. 2 illustrates time waveforms of various circuit parameters during normal operation of the conventional circuit of FIG. 1. Waveform (A) represents pulse width modulation signal PWM. Waveform (B) represents a voltage signal applied to the VGATE of signal responsive switch 20. Voltage at the VOUT node is shown in waveform (C). Voltage VITH at the output of error amplifier 22 is shown in waveform (D). In operation, at time t1, the PWM signal is high and switch 12 is closed so that the load is connected to ground. While in this condition, the switch 20 is switched at a peak current level, sensed as VSENSE=VITH, that is required to maintain voltage VOUT at a level equal to VREF. This circuit configuration functions in a well known manner as a current-mode voltage boost regulator, wherein VOUT is greater than VIN, and the error amplifier output directly controls the peak switching/inductor current. The switching of VGATE is implemented by the S-R latch 28 in response to the rising edge of oscillator 11, which sets the latch, raising VGATE and closing switch 20. Switch 20 is opened when VSENSE crosses the level of voltage VITH at capacitor 24, which crossing trips the output of comparator 15, resetting latch 28. Switch 20 is again closed at the next rising edge provided by oscillator 11. When switch 20 is in the closed state and switch 12 is in the closed state, charge on capacitor 14 discharges through the load 10. When switch 20 is in the open state and switch 12 is in the closed state, charge is applied to capacitor 14 from the power supply via diode 18. Voltage VOUT and voltage VITH are relatively constant in steady-state operation, as shown by waveforms (C) and (D), respectively.
At time t2 the PWM signal goes low to set switch 12 to an open state, causing instantaneous disconnection of the output load from ground. When the load current is interrupted, a VOUT overvoltage condition occurs as the supply continues to deliver excess output current through the inductance 16 to the output capacitor 14 during the duty cycle switching of switch 20. The VOUT overvoltage condition, as shown in waveform (C), continues until the feedback control loop has time to correct for the error. As excess output current is delivered to the output capacitor 14, VOUT increases. The increased feedback voltage (VREF−VOUT), applied to the error amplifier, decreases the charge applied to capacitor 24, as indicated by current waveform (D), thereby resulting in a decreased peak switching current at which switch 20 opens. The current IL is shown in waveform (E). The changes of voltages VOUT and VITH decrease toward a steady-state value as correction is made by the circuit for the transient effects of the PWM signal change. The time required to reach a new steady-state value is related to the closed-loop bandwidth and crossover frequency for the control loop.
At time t3 the PWM signal again goes high and the load is reconnected to ground through now-closed switch 12. At that time the periodic signal VGATE applied to switch 20 had been adjusted to supply the appropriate charge to capacitor 14 with the load disconnected. A VOUT undervoltage condition occurs upon reconnection of the load as it will discharge capacitor 14 because the peak current supplied by switch 20 at that time, as shown in waveform (E), is not appropriate to the changed condition. The undervoltage condition continues until the feedback control loop can correct and recharge the capacitor. The negative feedback voltage is acted upon by the feedback control loop to adjust the current limit imposed on switch 20 such that the charge applied to capacitor 14 is increased. Voltages VOUT and VITH increase toward their appropriate steady-state values as correction is made by the circuit for the transient effects of the PWM signal change.
The magnitude and time extents of the overvoltage and undervoltage conditions depend on control loop parameters, load conditions, and PWM switching frequency. Effective PWM control of a load is thus fundamentally limited to frequencies substantially below that at which the control loop can correct perturbations. The need thus exists for a pulse width modulated control arrangement for a switch-mode power supply that is operable at high frequencies.